CADD

Responding to msg by COR3622@xxxxxxx (Tracy Corcoran) on


To supplement the advice of others on CADD systems for the near
term, it is worth initiating familiarity with systems that are
coming through the pipeline for the future when you are a
wealthy architect-engineer-contractor, say like the top design
firms in the world (The Parsons Corp., the top of the 500
biggest designers, pulled in fees of $1.045 billion last year).


To pick up on Stephen's glowing remark about SGI, I attach a
mouth-watering description of the firms latest supercomputer
which is outselling all others around the world -- beating
Cray, NEC, IBM, and the Big Boy lot -- and totally compatible
with the consumer appliances at Coumbia.


Our firm hopes to get one of these soon.



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Power Challenge

The Power Challenge from Silicon Graphics Inc. (SGI) is a
symmetric
multiprocessor supercomputer based on the 64-bit MIPS R8000
Microprocessor. It is named odin. The NCSA configuration has
16 MIPS
R8000 processors and 4 gigabytes (Gbytes) of shared memory.

Each processor has a theoretical peak speed of 300 megaflops
(Mflops),
giving the machine a total peak speed of 4.8 gigaflops
(Gflops) in
16-processor dedicated mode. The operating system, IRIX 6.0,
is a
64-bit extension of the IRIX 5.2 operating system and is
based on
System V Release 4 UNIX with some BSD-like extensions.

The Power Challenge system is binary compatible with 32-bit
SGI
workstations, which are based on R4000-series
microprocessors. The
Power Challenge can compile executables for those machines
and also
run binary executables compiled on them.



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SILICON GRAPHICS INTRODUCES POWER CHALLENGEARRAY

Company Continues to Reinvent Supercomputing with New
Distributed Parallel
Processing System

On November 15, 1994, Silicon Graphics, Inc. announced its
plans to
introduce the POWER CHALLENGEarray(tm), a distributed
parallel
processing system powered by up to 144 MIPS(r) R8000(tm)
microprocessors to solve Grand Challenge-class problems. By
utilizing
a unique modular approach, the POWER CHALLENGEarray creates
a
highly-scalable supercomputing system that combines the
power of up to
eight POWER CHALLENGE(tm) symmetric multiprocessing (SMP)
supercomputing systems and provides over 43 GFLOPS of peak
performance.

The POWER CHALLENGEarray combines the efficiency,
flexibility and
programmability benefits of Silicon Graphics' shared memory
approach
with up to 128 GB of main memory, over 4 GB/sec of disk
transfer
capacity and over 63 terabytes of standard disk space. The
POWER
CHALLENGE supercomputing systems utilized in the POWER
CHALLENGEarray
shatter supercomputer price/performance levels and scale
from two to
18 processors, while delivering up to 5.4 GFLOPS of peak
performance
and the power of up to 18 Cray Y-MP(tm) class processors in
a single
RISC-based system. These systems are connected by
high-performance
interconnection technology such as HiPPI or FDDI. While the
cost of a
traditional supercomputer has restricted its use to major
research
laboratories and specialized facilities, POWER CHALLENGE
systems are
designed to be easy to deploy and use, enabling more
scientists and
technical professionals to focus on solving Grand
Challenge-class
problems.

The POWER CHALLENGEarray approach is unique among
distributed
computing models as each individual system that comprises
the array is
itself a parallel supercomputer. This leads to efficiencies
in the
computation-to-communication ratio because messages are sent
between
systems for much larger blocks of parallel processing. The
POWER
CHALLENGEarray is ideal for solving the world's most complex
supercomputing problems in areas such as computational fluid
dynamics,
structural dynamics, molecular dynamics, operations research
optimization techniques and seismic data processing projects
that were
previously unsolved or solved on expensive special-purpose
hardware.

"With the introduction of the POWER CHALLENGEarray, Silicon
Graphics
is continuing to redefine the rules of supercomputing by
providing
deployability and accessibility to powerful technology. The
POWER
CHALLENGEarray maximizes this strategy by taking advantage
of Silicon
Graphics' powerful shared-memory multiprocessing technology
to provide
a very intuitive and efficient method for users to exploit
parallelism," said Forest Baskett, Silicon Graphics' chief
technology
officer and senior vice president of research and
development. "The
scalability and cost-effectiveness of the POWER
CHALLENGEarray make it
a very unique tool for technical professionals who are in
the pursuit
of solving the Grand Challenges."

A POWER CHALLENGEarray can be configured with both the POWER
CHALLENGE
XL rack system with two to 18 R8000 MIPS microprocessors and
the POWER
CHALLENGE L deskside system, configured with one to six
R8000
microprocessors. All POWER CHALLENGE supercomputing systems
run
Silicon Graphics' IRIX(tm) 6.0 enhanced 64-bit version of
the UNIX(r)
operating system which includes a multi-threaded kernel.

The POWER CHALLENGEarray will be available by the end of Q2
1995.

Contact: Virginia Henderson (415) 390-1306

Silicon Graphics, Inc. is the leading manufacturer of
high-performance
visual computing systems. The company delivers interactive
three-dimensional graphics, digital media and
multiprocessing
supercomputing technologies to technical, scientific and
creative
professionals. Its subsidiary, MIPS Technologies, Inc.,
designs and
licenses the industry's leading RISC processor technology
for the
computer systems and embedded control markets. Silicon
Graphics has
offices worldwide and headquarters in Mountain View,
California.

Silicon Graphics, IRIS and the Silicon Graphics logo are
registered
trademarks, and POWER CHALLENGE, POWER CHALLENGEarray,
Challenge,
CHALLENGEarray IRIX are trademarks of Silicon Graphics,
Inc.; MIPS is
a registered trademark of MIPS Technologies, Inc. UNIX is a
registered
trademark of UNIX Systems Laboratories, Inc.; Cray Y-MP is a
trademark
of Cray Research, Inc.

Read how POWER CHALLENGEarray is to be Utilized for
Computational
AeroScience Projects.

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SILICON GRAPHICS SUPERCOMPUTING TECHNOLOGY POWER ADVANCED
AEROSPACE DESIGN AT
NASA AMES

POWER CHALLENGEarray to be Utilized for Computational
AeroScience Projects

On November 15, 1994, Silicon Graphics, Inc. announced that
NASA Ames
Numerical Aerodynamic Simulation (NAS) Facility has selected
the POWER
CHALLENGEarray(tm) distributed parallel processing system to
act as
part of a system software testbed for distributed computing.
Funded
through the national High Performance Computing and
Communications
(HPCC) Program, this project will enable NASA to develop
system
software to support Computational AeroScience (CAS) projects
focused
on assisting the aerospace industry in designing future
generations of
aerospace vehicles.

NASA has purchased 16 POWER CHALLENGE(tm) L supercomputers
all of
which incorporate the world's fastest supercomputing
microprocessor,
the MIPS(r) RISC R8000(tm). The POWER CHALLENGEarray
combines the
power of several POWER CHALLENGE systems connected by
high-speed
network connections, such as HiPPI and FDDI. The POWER
CHALLENGEarray
utilizes a modular approach to create a highly scalable
supercomputing
system ideal for solving Grand Challenge class problems in
areas such
as computational fluid dynamics, operations research
optimization
techniques and seismic data processing.

"NASA has experienced a long-term, mutually beneficial
relationship
with Silicon Graphics and has long utilized the company's
3D
visualization capabilities for development and applied
research in
scientific visualization," said Marisa Chancellor, acting
division
chief at NAS. "We envision the POWER CHALLENGEarray
playing a role
in assisting NAS as it continues to conduct research and
testing in
Computational Aerospace Projects."

The goal of the CAS project in the NASA HPCC Program is to
accelerate
the development and availability of high-performance
computing
technology that will be of use to the U.S. Aerospace
community.
Designers of the testbed will develop, integrate and test
system
software that makes a cluster of heterogeneous workstations
appear as
a single integrated environment and to develop
cost-effective parallel
CAS applications.

"NAS has continually pushed the envelope with its research
and
development of applications in aeronautical technology,"
said Ron
Bernal, vice president and general manager of Silicon
Graphics'
Supercomputing Systems Division. "By utilizing this
advanced
technology, NAS is shining a beacon into the future of
aerospace
design. We believe that many of the designs of
future-generation
aircraft will have their roots in the CAS project."

Several solutions from Silicon Graphics' Distributed
Powercomputing
Program will be utilized in the project. The initial
configuration
will use LSF 2.0 from Platform Computing as a load sharing
management
tool. Both PVM and MPI will also be used as message passing
libraries
over FDDI, HiPPI, ATM and Ethernet network connections.

The Numerical Aerodynamic Simulation program was started in
1984 to
maintain the role of the United States as a leader in
aeronautical
technology. NAS objectives are to act as a pathfinder in
advanced,
large scale computational capability through systematic
incorporation
of state-of-the-art improvements in computer hardware and
software
technologies; to provide a national computational
capability,
available to NASA, DOD, industry, other governmental
agencies and
universities, as a necessary element in ensuring continuing
leadership
in computational fluid dynamics and related computational
aerospace
disciplines; and to provide a strong research tool for the
Office of
Aeronautics within NASA itself.



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